// Multiple-cycle channel
module mc_channel(clock, d_in, d_out);
	parameter width = 16;
	parameter depth = 3;
	
	parameter addrwidth =
	( (((depth)) ==0) ? 0 // - depth==0 LOG2=0
			: (((depth-1)>>0)==0) ? 0 // - depth<=1 LOG2=0
			: (((depth-1)>>1)==0) ? 1 // - depth<=2 LOG2=1
			: (((depth-1)>>2)==0) ? 2 // - depth<=4 LOG2=2
			: (((depth-1)>>3)==0) ? 3 // - depth<=8 LOG2=3
			: (((depth-1)>>4)==0) ? 4 // - depth<=16 LOG2=4
			: (((depth-1)>>5)==0) ? 5 // - depth<=32 LOG2=5
			: (((depth-1)>>6)==0) ? 6 // - depth<=64 LOG2=6
			: (((depth-1)>>7)==0) ? 7 // - depth<=128 LOG2=7
			: 8) // - depth<=256 LOG2=8
			;
	
	input clock;
	
	input [width-1:0] d_in;
	output [width-1:0] d_out;
	
	reg [addrwidth-1:0] counter;
		
	
	reg [width-1:0] q [depth-1:0];
	
	always @(posedge clock) begin
	
		for(counter=depth-1; counter>0; counter=counter-1) begin
			q[counter] <= q[counter-1];
		end
		q[0] <= d_in;
		
	end
	
	assign d_out = q[depth-1];
	

	
endmodule 
